Functional Description
10.1.4
FSB Dynamic Bus Inversion
The GMCH supports Dynamic Bus Inversion (DBI) when driving and when receiving
data from the processor. DBI limits the number of data signals that are driven to a low
voltage on each quad pumped data phase. This decreases the worst-case power
consumption of the GMCH. HDINV[3:0]# indicate if the corresponding 16 bits of data
are inverted on the bus for each quad pumped data phase:
HDINV[3:0]#
Data Bits
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HD[15:0]#
HD[31:16]#
HD[47:32]#
HD[63:48]#
Whenever the processor or the GMCH drives data, each 16-bit segment is analyzed. If
more than 8 of the 16 signals would normally be driven low on the bus, the
corresponding HDINV# signal will be asserted, and the data will be inverted prior to
being driven on the bus. Whenever the processor or the GMCH receives data, it
monitors HDINV[3:0]# to determine if the corresponding data segment should be
inverted.
10.1.5
APIC Cluster Mode Support
APIC Cluster mode support is required for backwards compatibility with existing
software, including various operating systems. As one example, beginning with
Microsoft Windows 2000, there is a mode (boot.ini) that allows an end user to enable
the use of cluster addressing support of the APIC.
•
The GMCH supports three types of interrupt re-direction:
⎯
⎯
⎯
Physical
Flat-Logical
Clustered-Logical
Datasheet
283
INTEL [ INTEL ]
