Integrated Graphics Device Registers (D2:F0,F1)
8.2.26
PMCAP—Mirror of Fun 0 Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/1/PCI
D2–D3h
0022h
RO
Size:
16 bits
This register is a Mirror of Function 0 with the same read/write attributes. The
hardware implements a single physical register common to both functions 0 and 1.
Bit
Access &
Default
Description
15:11
PME Support (PMES): This field indicates the power states in which
the IGD may assert PME#. Hardwired to 0 to indicate that the IGD
does not assert the PME# signal.
RO
00h
10
9
D2 Support (D2): The D2 power management state is not
supported. This bit is hardwired to 0.
RO
0b
D1 Support (D1): Hardwired to 0 to indicate that the D1 power
management state is not supported.
RO
0b
8:6
5
Reserved
RO
000b
Device Specific Initialization (DSI): Hardwired to 1 to indicate
that special initialization of the IGD is required before generic class
device driver is to use it.
RO
1b
4
3
Reserved
RO
0b
PME Clock (PMECLK): Hardwired to 0 to indicate IGD does not
support PME# generation.
RO
0b
2:0
Version (VER): Hardwired to 010b to indicate that there are 4 bytes
of power management registers implemented and that this device
complies with revision 1.1 of the PCI Power Management Interface
Specification.
RO
010b
264
Datasheet
INTEL [ INTEL ]
