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317607-001 参数 Datasheet PDF下载

317607-001图片预览
型号: 317607-001
PDF下载: 下载PDF文件 查看货源
内容描述: Express芯片组 [Express Chipset]
分类和应用:
文件页数/大小: 351 页 / 2481 K
品牌: INTEL [ INTEL ]
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Integrated Graphics Device Registers (D2:F0,F1)  
8.2.9  
HDR2—Header Type  
B/D/F/Type:  
Address Offset:  
Default Value:  
Access:  
0/2/1/PCI  
0Eh  
80h  
RO  
8 bits  
Size:  
This register contains the Header Type of the IGD.  
Bit  
Access &  
Default  
Description  
7
Multi Function Status (MFUNC): Indicates if the device is a Multi-  
Function Device. The Value of this register is determined by Device 0,  
offset 54h, DEVEN[4]. If Device 0 DEVEN[4] is set, the MFUNC bit is  
also set.  
RO  
1b  
6:0  
Header Code (H): This is a 7-bit value that indicates the Header Code  
for the IGD. This code has the value 00h, indicating a type 0  
configuration space format.  
RO  
00h  
8.2.10  
MMADR—Memory Mapped Range Address  
B/D/F/Type:  
Address Offset:  
Default Value:  
Access:  
0/2/1/PCI  
10–13h  
00000000h  
RW, RO  
Size:  
64 bits  
This register requests allocation for the IGD registers and instruction ports. The  
allocation is for 512 KB and the base address is defined by bits 31:19.  
Bit  
63:36  
35:20  
18:4  
3
Access &  
Default  
Description  
RO  
0s  
RW  
0000h  
Memory Base Address (MBA): Set by the OS, these bits correspond  
to address signals 35:19.  
RO  
0000h  
Address Mask (ADMSK): Hardwired to 0s to indicate 512 KB address  
range.  
RO  
0b  
Prefetchable Memory (PREFMEM): Hardwired to 0 to prevent  
prefetching.  
2:1  
RO  
Memory Type (MEMTYP): Hardwired to 0s to indicate 32-bit  
00b  
address.  
0
RO  
0b  
Memory / IO Space (MIOS): Hardwired to 0 to indicate memory  
space.  
254  
Datasheet