Integrated Graphics Device Registers (D2:F0,F1)
8.2.13
ROMADR—Video BIOS ROM Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/1/PCI
30–33h
00000000h
RO
Size:
32 bits
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s.
Bit
31:18
17:11
10:1
0
Access &
Default
Description
RO
0000h
ROM Base Address (RBA): Hardwired to 0s.
RO
00h
Address Mask (ADMSK): Hardwired to 0s to indicate 256 KB address
range.
RO
000h
Reserved. Hardwired to 0s.
RO
0b
ROM BIOS Enable (RBE):
0 = ROM not accessible.
8.2.14
CAPPOINT—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/1/PCI
34h
D0h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
D0h
Capabilities Pointer Value (CPV): This field contains an offset into
the function's PCI Configuration Space for the first item in the New
Capabilities Linked List, the MSI Capabilities ID registers at address
90h or the Power Management capability at D0h.
This value is determined by the configuration in CAPL[0].
256
Datasheet
INTEL [ INTEL ]
