Integrated Graphics Device Registers (D2:F0,F1)
8.2.7
CLS—Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/1/PCI
0Ch
00h
RO
8 bits
Size:
The IGD does not support this register as a PCI slave.
Bit
Access &
Default
Description
7:0
Cache Line Size (CLS): This field is hardwired to 0s. The IGD as a
PCI compliant master does not use the Memory Write and Invalidate
command and, in general, does not perform operations based on
cache line size.
RO
00h
8.2.8
MLT2—Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/1/PCI
Dh
00h
RO
8 bits
Size:
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
Bit
Access &
Default
Description
7:0
Master Latency Timer Count Value (MLTCV): Hardwired to 0s.
RO
00h
Datasheet
253
INTEL [ INTEL ]
