Integrated Graphics Device Registers (D2:F0,F1)
8.1.15
CAPPOINT—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
34h
90h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
90h
Capabilities Pointer Value (CPV): This field contains an offset into
the function's PCI Configuration Space for the first item in the New
Capabilities Linked List, the MSI Capabilities ID registers at address
90h or the Power Management capability at D0h.
This value is determined by the configuration in CAPL[0].
8.1.16
INTRLINE—Interrupt Line
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
3Ch
00h
RW
Size:
8 bits
Bit
Access &
Default
Description
7:0
RW
00h
Interrupt Connection (INTCON): This field is used to
communicate interrupt line routing information. POST software
writes the routing information into this register as it initializes and
configures the system. The value in this register indicates to which
input of the system interrupt controller the device's interrupt pin is
connected.
8.1.17
INTRPIN—Interrupt Pin
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
3Dh
01h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
Interrupt Pin (INTPIN): As a single function device, the IGD
01h
specifies INTA# as its interrupt pin.
01h = INTA#.
234
Datasheet
INTEL [ INTEL ]
