Integrated Graphics Device Registers (D2:F0,F1)
8.1.11
IOBAR—I/O Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
20–23h
00000001h
RO, RW
Size:
32 bits
This register provides the Base offset of the I/O registers within Device 2. Bits 15:3
are programmable allowing the I/O Base to be located anywhere in 16 bit I/O Address
Space. Bits 2:1 are fixed and return zero; bit 0 is hardwired to a one indicating that 8
bytes of I/O space are decoded. Access to the 8Bs of I/O space is allowed in PM state
D0 when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1–D3 or if
I/O Enable is clear or if Device 2 is turned off or if Internal graphics is disabled thru
the fuse or fuse override mechanisms.
Note that access to this IO BAR is independent of VGA functionality within Device 2.
Also note that this mechanism is available only through function 0 of Device 2 and is
not duplicated in function 1.
If accesses to this IO bar is allowed then the GMCH claims all 8, 16 or 32 bit I/O
cycles from the processor that falls within the 8B claimed.
Bit
31:16
15:3
2:1
Access &
Default
Description
Reserved
RO
0000h
IO Base Address (IOBASE): Set by the OS, these bits correspond
RW
0000h
to address signals 15:3.
Memory Type (MEMTYPE): Hardwired to 0s to indicate 32-bit
RO
00b
address.
0
Memory/IO Space (MIOS): Hardwired to 1 to indicate I/O space.
RO
1b
8.1.12
SVID2—Subsystem Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
2C–2Dh
0000h
RWO
16 bits
Size:
Bit
Access &
Default
Description
15:0
Subsystem Vendor ID (SUBVID): This value is used to identify the
vendor of the subsystem. This register should be programmed by BIOS
during boot-up. Once written, this register becomes Read Only. This
register can only be cleared by a Reset.
RWO
0000h
232
Datasheet
INTEL [ INTEL ]
