Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
List of Tables
1
Processor Identification.......................................................................................11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
System Bus Clock in Deep Sleep Mode (Differential Mode only) .......................16
Voltage Identification Definition ..........................................................................20
System Bus Signal Groups ................................................................................23
Frequency Select Truth Table for BSEL[1:0] ......................................................24
Absolute Maximum Ratings ................................................................................25
Voltage and Current Specifications.....................................................................26
Power Supply Current Slew Rate (dIcccore/dt)...................................................27
Vcc Static & Transient Tolerance........................................................................28
AGTL Signal Group Levels Specifications ..........................................................29
Non-AGTL Signal Group Levels Specifications ..................................................29
3.3 Volt CMOS Output Signal Group DC Specifications.....................................30
Processor AGTL Bus Specifications ...................................................................30
System Bus Timing Specifications (Single-Ended Clock)...................................31
System Bus Timing Specifications (Differential Clock) .......................................32
Valid System Bus to Core Frequency Ratios .....................................................33
System Bus Timing Specifications (AGTL Signal Group) ...................................33
System Bus Timing Specifications (CMOS Signal Group)..................................33
System Bus Timing Specifications (Reset Conditions) ......................................34
System Bus Timing Specifications (APIC Clock and APIC I/O)..........................34
System Bus Timing Specifications (TAP Connection) ........................................35
Platform Power-On Timings................................................................................36
BCLK (Single-Ended Clock Mode) Signal Quality Specifications for
Simulation at the Processor Pins ........................................................................41
24
25
BCLK/BCLK# (Differential Clock Mode) and PICCLK Signal Quality
Specifications for Simulation at the Processor Pins............................................41
AGTL Signal Groups Ringback Tolerance Specifications at the
Processor Pins....................................................................................................42
Example Platform Information.............................................................................45
100 MHz AGTL Signal Group Overshoot/Undershoot Tolerance ......................46
33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance........................48
Signal Ringback Specifications for Non-AGTL Signal Simulation at the
26
27
28
29
Processor Pins....................................................................................................49
Processor Thermal Design Power .....................................................................51
THERMTRIP# Time Requirement.......................................................................51
Thermal Diode Parameters.................................................................................52
Thermal Diode Interface......................................................................................52
The Processor Package Dimensions..................................................................54
Processor Case Loading Parameters .................................................................54
Signal Listing in Order by Signal Name ..............................................................58
Signal Listing in Order by Pin Number................................................................63
Boxed Processor Fan Heatsink Spatial Dimensions...........................................70
Fan Heatsink Power and Signal Specifications...................................................72
Signal Description ...............................................................................................73
Output Signals.....................................................................................................80
Input Signals .......................................................................................................80
Input/Output Signals (Single Driver)....................................................................81
Input/Output Signals (Multiple Driver) .................................................................82
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
6
Datasheet
INTEL [ INTEL ]
