Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
List of Figures
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Integrated Heat Spreader (IHS) ............................................................................9
AGTL Bus Topology in a Uniprocessor Configuration.........................................14
Stop Clock State Machine...................................................................................14
PLL Filter Specification........................................................................................18
Differential/Single-Ended Clocking Example.......................................................19
VTT Power Good and Bus Select Interconnect Diagram.....................................21
BSEL[1:0] Example for a System Design............................................................24
Vcc Static and Transient Tolerance ....................................................................28
Clock Waveform..................................................................................................36
BCLK/BCLK#, PICCLK, and TCK Generic Clock Waveform ..............................37
System Bus Valid Delay Timings ........................................................................37
System Bus Setup and Hold Timings..................................................................38
System Bus Reset and Configuration Timings....................................................38
Platform Power-On Sequence and Timings........................................................39
Power-On Reset and Configuration Timings.......................................................39
Test Timings (TAP Connection) ..........................................................................40
Test Reset Timings .............................................................................................40
BCLK/BCLK#, PICCLK Generic Clock Waveform at the Processor Pins ...........42
Low to High AGTL Receiver Ringback Tolerance...............................................43
Maximum Acceptable AGTL Overshoot/Undershoot Waveform.........................47
Non-AGTL Overshoot/Undershoot, Settling Limit, and Ringback ......................47
Noise Estimation .................................................................................................50
Package Dimensions...........................................................................................53
Volumetric Keep-Out...........................................................................................55
Component Keep-Out .........................................................................................55
Top Side Processor Markings .............................................................................56
Processor Pinout................................................................................................57
Conceptual Boxed Processor for the PGA370 Socket........................................68
Comparison between FC-PGA and FC-PGA2 package......................................69
Side View of Space Requirements for the Boxed Processor ..............................69
Dimensions of Mechanical Step Feature in Heatsink Base.................................70
Thermal Airspace Requirement for all Boxed Processor Fan
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Heatsinks in the PGA370 Socket ........................................................................71
Boxed Processor Fan Heatsink Power Cable Connector Description.................72
Motherboard Power Header Placement Relative to the Boxed Processor..........72
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Datasheet
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INTEL [ INTEL ]
