Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Contents
1.0
Introduction.........................................................................................................................9
1.1
Terminology.........................................................................................................10
1.1.1 Package and Processor Terminology ....................................................10
1.1.2 Processor Naming Convention...............................................................11
Related Documents.............................................................................................12
1.2
2.0
Electrical Specifications....................................................................................................13
2.1
2.2
Processor System Bus and VREF .......................................................................................... 13
Clock Control and Low Power States..................................................................14
2.2.1 Normal State—State 1 ...........................................................................15
2.2.2 AutoHALT Powerdown State—State 2...................................................15
2.2.3 Stop-Grant State—State 3 .....................................................................15
2.2.4 HALT/Grant Snoop State—State 4 ........................................................15
2.2.5 Sleep State—State 5..............................................................................16
2.2.6 Deep Sleep State—State 6 ....................................................................16
2.2.7 Clock Control..........................................................................................17
Power and Ground Pins ......................................................................................17
2.3.1 Phase Lock Loop (PLL) Power...............................................................17
Decoupling Guidelines ........................................................................................18
2.4.1 Processor VCCCORE Decoupling............................................................18
Processor System Bus Clock and Processor Clocking.......................................19
Voltage Identification...........................................................................................19
Processor System Bus Unused Pins...................................................................21
Processor System Bus Signal Groups ................................................................22
2.8.1 Asynchronous vs. Synchronous for System Bus Signals.......................23
2.8.2 System Bus Frequency Select Signals ..................................................24
Test Access Port (TAP) Connection....................................................................25
Maximum Ratings................................................................................................25
Processor Voltage Level Specifications ..............................................................25
AGTL System Bus Specifications........................................................................30
System Bus Timing Specifications ......................................................................31
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
3.0
Signal Quality Specifications............................................................................................41
3.1
BCLK/BCLK# & PICCLK Signal Quality Specifications and
Measurement Guidelines ....................................................................................41
AGTL Signal Quality Specifications and Measurement Guidelines.....................42
3.2.1 Overshoot/Undershoot Guidelines .........................................................43
3.2.2 Overshoot/Undershoot Magnitude .........................................................44
3.2.3 Overshoot/Undershoot Pulse Duration...................................................44
3.2.4 Activity Factor.........................................................................................44
3.2.5 Reading Overshoot/Undershoot Specification Tables............................45
3.2.6 Determining if a System Meets the Overshoot/Undershoot
3.2
Specifications .........................................................................................46
Non-AGTL Signal Quality Specifications and Measurement Guidelines.............47
3.3.1 Overshoot/Undershoot Guidelines .........................................................48
3.3.2 Ringback Specification...........................................................................48
3.3.3 Settling Limit Guideline...........................................................................49
3.3
Datasheet
3
INTEL [ INTEL ]
