E
FAST BOOT BLOCK DATASHEET
VIH
CLK (C)
Note 1
VIL
R4
VIH
Valid
Address
A19-0 (A)
VIL
R9
R18
R11
R17
VIH
VIL
ADV# (V)
R16
R5
R22
VIH
VIL
CE# (E)
R12
R6
VIH
OE# (G)
VIL
VIH
WE# (W)
VIL
VOH
WAIT# (T)
VOL
R20
R7
R23
VOH
VOL
High Z
Valid
Output
DQ15-0 (D/Q)
NOTE:
1. Depending upon the frequency configuration code value in the read configuration register, insert clock cycles:
• Frequency Configuration 2 insert two clock cycles
• Frequency Configuration 3 insert three clock cycles
• Frequency Configuration 4 insert four clock cycles
• Frequency Configuration 5 insert five clock cycles
• Frequency Configuration 6 insert six clock cycles
See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 16. AC Waveform for Single Synchronous Read Operations
from Parameter Blocks, Status Register, Identifier Codes
35
PRODUCT PREVIEW
INTEL [ INTEL ]
