FAST BOOT BLOCK DATASHEET
E
(1,6)—
8.5
AC Characteristics—Read-Only Operations
Extended Temperature
Product
–95
3.0 V–3.6 V 2.7 V–3.6 V 2.7 V–3.6 V
Notes Min Max Min Max Min Max Unit
–120
VCC
#
Sym
Parameter
CLK Period
R1 tCLK
R2 tCH(tCL
R3 tCHCL
R4 tAVCH
R5 tVLCH
R6 tELCH
R7 tCHQV
R8 tCHQX
R9 tCHAX
R10 tCHTL
R11 tAVVH
R12 tELVH
R13 tAVQV
R14 tELQV
R15 tVLQV
R16 tVLVH
R17 tVHVL
R18 tVHAX
R19 tAPA
R20 tGLQV
R21 tRHQV
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
CLK High (Low) Time
2.5
2.5
2.5
CLK Fall (Rise) Time
5
5
5
Address Valid Setup to CLK
ADV# Low Setup to CLK
CE# Low Setup to CLK
CLK to Output Delay
7
7
7
7
7
7
7
7
7
14
13
16
16
23
23
Output Hold from CLK
5
5
5
Address Hold from CLK
CLK to WAIT# delay
3
5
10
10
10
Address Setup to ADV# High
CE# Low to ADV# High
Address to Output Delay
CE# Low to Output Delay
ADV# Low to Output Delay
ADV# Pulse Width Low
ADV# Pulse Width High
Address Hold from ADV# High
Page Address Access Time
OE# Low to Output Delay
RST# High to Output Delay
10
10
10
10
10
10
90
90
90
95
95
95
120 ns
120 ns
120 ns
ns
2
10
10
3
10
10
3
10
10
3
4
3
ns
ns
21
25
23
25
30
30
ns
ns
600
25
600
25
600 ns
R22 tEHQZ
tGHQZ
CE# or OE# High to Output in
High Z, Whichever Occurs First
4
4
25
ns
R23 tOH
Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First
0
0
0
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.
2. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV
.
3. Address hold in synchronous burst-mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first.
4. Sampled, not 100% tested.
5. Output loading on WAIT# equals 15 pF.
6. Data bus voltage must be less than or equal to VCCQ when a read operation is initiated to guarantee AC specifications.
32
PRODUCT PREVIEW
INTEL [ INTEL ]
