FAST BOOT BLOCK DATASHEET
E
VIH
CLK (C)
VIL
Note 1
R4
VIH
Valid
A19-0 (A)
Address
VIL
R9
R18
R11
R17
VIH
ADV# (V)
VIL
R16
R22
R5
VIH
CE# (E)
VIL
R12
R6
VIH
OE# (G)
VIL
VIH
WE# (W)
VIL
VOH
WAIT# (T)
VOL
R20
R7
R8
R23
VOH
High Z
Valid
Valid
Valid
Valid
DQ15-0 (D/Q)
Output
Output
Output
Output
VOL
NOTE:
1. Depending upon the frequency configuration code value in the read configuration register, insert clock cycles:
• Frequency Configuration 2 insert two clock cycles
• Frequency Configuration 3 insert three clock cycles
• Frequency Configuration 4 insert four clock cycles
• Frequency Configuration 5 insert five clock cycles
• Frequency Configuration 6 insert six clock cycles
See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 17. AC Waveform for Synchronous Burst Read Operations, Four Word Burst Length,
from Main Blocks
36
PRODUCT PREVIEW
INTEL [ INTEL ]
