FAST BOOT BLOCK DATASHEET
E
Read operations from the parameter blocks,
identifier codes and status register transpire as
single asynchronous or synchronous read cycles.
The read configuration register setting determines
whether or not read operations are asynchronous or
synchronous.
3.0 PRINCIPLES OF OPERATION
The Fast Boot Block flash memory components
include an on-chip WSM to manage block erase
and program. It allows for CMOS-level control
inputs, fixed power supplies, and minimal processor
overhead with RAM-like interface timings.
For all read operations, CE# must be driven active
to enable the devices, ADV# must be driven low to
open the internal address latch, and OE# must be
driven low to activate the outputs. In asynchronous
mode, the address is latched when ADV# is driven
high. In synchronous mode, the address is latched
by ADV# going high or ADV# low in conjunction
with a rising (falling) clock edge, whichever occurs
first. WE# must be at VIH. Figures 14 through 19
illustrate different read cycles.
3.1
Bus Operations
All bus cycles to and from flash memory conform to
standard microprocessor bus cycles.
3.1.1
READ
The flash memory has three read modes available:
read array, identifier codes, and status register.
These modes are accessible independent of the
VPP voltage. The appropriate read command (Read
Array, Read Identifier Codes, or Read Status
Register) must be written to the CUI to enter the
requested read mode. Upon initial power-up or exit
from reset, the device defaults to read array mode.
3.1.2
OUTPUT DISABLE
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0–DQ15 are
placed in a high-impedance state.
3.1.3
STANDBY
When reading information from main blocks in read
array mode, the device supports two high-
performance read configurations: asynchronous
Deselecting the device by bringing CE# to a logic-
high level (VIH) places the device in standby mode,
which substantially reduces device power
consumption. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operation, the
device continues to consume active power until the
program or erase operation is complete.
page-mode
and
synchronous
burst-mode.
Asynchronous page-mode is the default state and
provides high data transfer rate for non-clocked
memory subsystems. In this state, data is internally
read and stored in a high-speed page buffer. A1:0
addresses data in the page buffer. The page size is
four words. The other read configuration,
synchronous burst-mode, is enabled by writing to
read configuration register. This register sets the
read configuration, burst order, frequency
configuration, and burst length. In synchronous
burst-mode, the device latches the initial address
then outputs a sequence of data with respect to the
input CLK and read configuration setting.
3.1.4
WRITE
Commands are written to the CUI using standard
microprocessor write timings when ADV#, WE#,
and CE# are active and OE# inactive. The CUI
does not occupy an addressable memory location.
The address is latched on the rising edge of ADV#,
WE#, or CE# (whichever occurs first) and data
needed to execute a command is latched on the
rising edge of WE# or CE# (whichever goes high
first). Write operations are asynchronous.
Therefore, CLK is ignored during write operations.
Figure 20 illustrates a write operation.
12
PRODUCT PREVIEW
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