E
Sym
V
PP
Type
SUPPLY
V
CC
SUPPLY
V
CCQ
SUPPLY
FAST BOOT BLOCK DATASHEET
Table 1. Pin Descriptions
Name and Function
BLOCK ERASE AND PROGRAM POWER SUPPLY (2.7 V–3.6 V,
11.4 V–12.6 V):
For erasing array blocks or programming data, a valid voltage
must be applied to this pin. With V
PP
≤
V
PPLK
, memory contents cannot be altered.
Block erase and program with an invalid V
PP
voltage should not be attempted.
Applying 11.4 V–12.6 V to V
PP
can only be done for a maximum of 1000 cycles on
main blocks and 2500 cycles on the parameter blocks. V
PP
may be connected to
12 V for a total of 80 hours maximum (see Section 6.0 for details).
DEVICE POWER SUPPLY (2.7 V–3.6 V):
With V
CC
≤
V
LKO
, all write attempts to
the flash memory are inhibited. Device operations at invalid V
CC
voltages should
not be attempted.
OUTPUT POWER SUPPLY (1.65 V–2.5 V, 2.7 V–3.6 V):
Enables all outputs to be
driven to 1.65 V to 2.5 V or 2.7 V to 3.6 V. When V
CCQ
equals 1.65 V–2.5 V, V
CC
voltage must not exceed 3.3 V and should be regulated to 2.7 V–2.85 V to achieve
lowest power operation (see
DC Characteristics
for detailed information).
This input may be tied directly to V
CC
.
GND
NC
SUPPLY
GROUND:
Do not float any ground pins.
NO CONNECT:
Lead is not internally connected; it may be driven or floated.
2.3
Memory Blocking Organization
The Fast Boot Block flash memory family is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash device. For the address locations of each
block, see the memory maps in Figure 3 (top boot
blocking) and Figure 4 (bottom boot blocking).
2.3.1
PARAMETER BLOCKS
normally be stored in an EEPROM. By using
software techniques, the word-rewrite functionality
of EEPROMs can be emulated. Each 8- and
16-Mbit
device
contains
eight
4-Kwords
(4,096-words) parameter blocks.
2.3.2
MAIN BLOCKS
The Fast Boot Block flash memory architecture
includes parameter blocks to facilitate storage of
frequently updated small parameters that would
After the parameter blocks, the remainder of the
array is divided into equal size main blocks for code
and/or data storage. The 8-Mbit device contains
fifteen 32-Kword (32,768-word) main blocks, and
the 16-Mbit device contains thirty-one 32-Kword
(32,768-word) main blocks.
PRODUCT PREVIEW
9
INTEL [ INTEL CORPORATION ]
