FAST BOOT BLOCK DATASHEET
E
Table 1. Pin Descriptions
Name and Function
Sym
A
0
–A
19
Type
INPUT
ADDRESS INPUTS:
Inputs for addresses during read and write operations.
Addresses are internally latched during read and write cycles.
8-Mbit: A
0–18
, 16-Mbit: A
0–19
DQ
0
–
DQ
15
INPUT/
OUTPUT
DATA INPUT/OUTPUTS:
Inputs data and commands during write cycles, outputs
data during memory array, status register (DQ
0
–DQ
7
), and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or outputs
are disabled. Data is internally latched during a write cycle.
CLOCK:
Synchronizes the flash memory to the system operating frequency during
synchronous burst-mode read operations. When configured for synchronous burst-
mode reads, address is latched on the first rising (or falling, depending upon the
read configuration register setting) CLK edge when ADV# is active or upon a rising
ADV# edge, whichever occurs first. CLK is ignored during asynchronous page-
mode read and write operations.
ADDRESS VALID:
Indicates that a valid address is present on the address inputs.
Addresses are latched on the rising edge of ADV# during read and write
operations. ADV# may be tied active during asynchronous read and write
operations.
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption
to standby levels.
RESET:
When driven low, RST# inhibits write operations which provides data
protection during power transitions, and it resets internal automation. RST#-high
enables normal operation. Exit from reset sets the device to asynchronous read
array mode.
OUTPUT ENABLE:
Gates data outputs during a read cycle.
WRITE ENABLE:
Controls writes to the CUI and array. Addresses and data are
latched on the rising edge of the WE# pulse.
WRITE PROTECTION:
Provides a method for locking and unlocking all main
blocks and two parameter blocks.
When WP# is at logic low, lockable blocks are locked. If a program or erase
operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5
[block erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and can be
programmed or erased.
CLK
INPUT
ADV#
INPUT
CE#
INPUT
RST#
INPUT
OE#
WE#
WP#
INPUT
INPUT
INPUT
WAIT#
OUTPUT
WAIT:
Provides data valid feedback when configured for synchronous burst-mode
and the burst length is set to continuous. This signal is gated by OE# and CE# and
is internally pull-up to V
CCQ
via a resistor. WAIT# from several components can be
tied together to form one system WAIT# signal.
8
PRODUCT PREVIEW
INTEL [ INTEL CORPORATION ]
