FAST BOOT BLOCK DATASHEET
E
Table 3. Command Definitions(1)
Bus Cycles
First Bus Cycle
Second Bus Cycle
Command
Read Array/Reset
Req’d.
Notes Oper(2) Addr(3) Data(4) Oper(2) Addr(3) Data(4)
1
≥ 2
2
Write
Write
Write
Write
Write
Write
X
X
X
X
X
X
FFH
90H
70H
50H
20H
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
5
Read
Read
IA
ID
X
SRD
1
2
6,7
Write
Write
BA
D0H
WD
Program
2
6,7,8
40H
or
WA
10H
Block Erase and Program
Suspend
1
1
2
6
6
Write
Write
Write
X
X
X
B0H
D0H
60H
Block Erase and Program
Resume
Set Read Configuration
Write
RCD
03H
NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
2. Bus operations are defined in Table 2.
3. X = Any valid address within the device.
IA = Identifier Code Address.
BA = Address within the block being erased.
WA = Address of memory location to be written.
RCD = Data to be written to the read configuration register. This data is presented to the device on A15-0; set all other
address inputs to “0.”
4. SRD = Data read from status register. See Table 5 for a description of the status register bits.
WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes. See Table 4 for manufacturer and device codes.
RCD = Data to be written to read configuration register. SeeTable 6 for a description of the read configuration register bits.
5. Following the Read Identifier Codes command, read operations access manufacturer, device codes, and read
configuration register.
6. Following a block erase, program, and suspend operation, read operations access the status register.
7. To issue a block erase, program, or suspend operation to a lockable block, hold WP# at V .
IH
8. Either 40H or 10H are recognized by the WSM as the program setup.
14
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