E
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
(3,4)
6.7
Block Erase, Program, and Lock-Bit Configuration Performance
#
Sym
Parameter
Notes
Min
Typ(1)
Max
Unit
W16 tWHQV1
tEHQV1
Write Buffer Byte Program Time
2,5
TBD
6
TBD
µs
W16 tWHQV2
tEHQV2
Write Buffer Word Program Time
2,5
2
TBD
TBD
TBD
TBD
TBD
TBD
12
120
0.8
1.0
12
TBD
TBD
TBD
TBD
TBD
TBD
35
µs
µs
W16 tWHQV3
tEHQV3
Byte Program Time (Using
Word/Byte Program Command)
Block Program Time (Using Write
to Buffer Command)
2
sec
sec
µs
W16 tWHQV4
tEHQV4
Block Erase Time
2
W16 tWHQV5
tEHQV5
Set Lock-Bit Time
2
W16 tWHQV6
tEHQV6
Clear Block Lock-Bits Time
2
1.5
25
sec
µs
W16 tWHRH
tEHRH
Erase Suspend Latency Time to
Read
NOTES:
1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speedversions.
4. Sampled but not 100% tested.
5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
51
ADVANCE INFORMATION
INTEL [ INTEL ]
