INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
V
IH
STS (R)
VIL
P2
VIH
RP# (P)
VIL
P1
0606_18
NOTES:
STS is shown in its default mode (RY/BY#).
Figure 18. AC Waveform for Reset Operation
Reset Specifications(1)
#
Sym.
Parameter
Notes Min Max Unit
P1
tPLPH
RP# Pulse Low Time
(If RP# is tied to VCC, this specification is not applicable)
2
35
µs
P2
tPHRH RP# High to Reset during Block Erase, Program, or
Lock-Bit Configuration
3
100
ns
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum
required RP# Pulse Low Time is 100 ns.
3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
50
ADVANCE INFORMATION
INTEL [ INTEL ]
