INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
5.0 DESIGN CONSIDERATIONS 5.3 Power Supply Decoupling
5.1 Three-Line Output Control
E
Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE0, CE1, CE2, and OE#. Transient
current magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Since Intel
StrataFlash memory devices draw their power from
three VCC pins (these devices do not include a VPP
pin), it is recommended that systems without
separate power and ground planes attach a 0.1 µF
ceramic capacitor between each of the device’s
three VCC pins (this includes VCCQ) and ground.
These high-frequency, low-inductance capacitors
should be placed as close as possible to package
leads on each StrataFlash device. Each device
should have a 0.1 µF ceramic capacitor connected
between its VCC and GND. These high-frequency,
low inductance capacitors should be placed as
close as possible to package leads. Additionally, for
every eight devices, a 4.7 µF electrolytic capacitor
should be placed between VCC and GND at the
array’s power supply connection. The bulk capacitor
will overcome voltage slumps caused by PC board
trace inductance.
The device will often be used in large memory
arrays. Intel provides five control inputs (CE0, CE1,
CE2, OE#, and RP#) to accommodate multiple
memory connections. This control provides for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus
contention will not occur.
To use these control inputs efficiently, an address
decoder should enable the device (see Table 2,
Chip Enable Truth Table) while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while de-
selected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2
STS and Block Erase, Program,
and Lock-Bit Configuration
Polling
5.4
V
, V
, RP# Transitions
STS is an open drain output that should be
connected to VCCQ by a pull-up resistor to provide a
hardware method of detecting block erase,
program, and lock-bit configuration completion. In
default mode, it transitions low after block erase,
program, or lock-bit configuration commands and
returns to High Z when the WSM has finished
executing the internal algorithm. For alternate
configurations of the STS pin, see the Configuration
command.
CC PEN
Block erase, program, and lock-bit configuration are
not guaranteed if VPEN or VCC falls outside of the
specified operating ranges, or RP# ≠ VIH or VHH. If
RP# transitions to VIL during block erase, program,
or lock-bit configuration, STS (in default mode) will
remain low for a maximum time of tPLPH + tPHRH
until the reset operation is complete. Then, the
operation will abort and the device will enter
reset/power-down mode. The aborted operation
may leave data partially corrupted after
programming, or partially altered after an erase or
lock-bit configuration. Therefore, block erase and
lock-bit configuration commands must be repeated
after normal operation is restored. Device power-off
or RP# = VIL clears the status register.
STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
STS, in default mode, is also High Z when the
device is in block erase suspend (with programming
inactive) or in reset/power-down mode.
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ADVANCE INFORMATION
INTEL [ INTEL ]
