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28F320B3 参数 Datasheet PDF下载

28F320B3图片预览
型号: 28F320B3
PDF下载: 下载PDF文件 查看货源
内容描述: 智能3高级启动块4-, 8-,16- , 32兆位闪存系列 [SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY]
分类和应用: 闪存
文件页数/大小: 48 页 / 296 K
品牌: INTEL [ INTEL ]
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SMART 3 ADVANCED BOOT BLOCK  
E
When VPP < VPPLK, the device will only execute the  
following commands successfully: Read Array,  
Read Status Register, Clear Status Register and  
Read Identifier. The device provides standard  
EEPROM read, standby and output disable  
operations. Manufacturer identification and device  
identification data can be accessed through the  
CUI. All functions associated with altering memory  
contents, namely program and erase, are  
accessible via the CUI. The internal Write State  
Machine (WSM) completely automates program  
and erase operations while the CUI signals the start  
of an operation and the status register reports  
status. The CUI handles the WE# interface to the  
data and address latches, as well as system status  
requests during WSM operation.  
3.1  
Bus Operation  
Smart  
3 Advanced Boot Block flash memory  
devices read, program and erase in-system via the  
local CPU or microcontroller. All bus cycles to or  
from the flash memory conform to standard  
microcontroller bus cycles. Four control pins dictate  
the data flow in and out of the flash component:  
CE#, OE#, WE# and RP#. These bus operations  
are summarized in Table 3.  
Table 3. Bus Operations(1)  
Mode  
Note  
RP#  
CE#  
OE#  
WE#  
DQ0–7  
DQ8–15  
Read (Array, Status, or  
Identifier)  
2–4  
VIH  
VIL  
VIL  
VIH  
DOUT  
DOUT  
Output Disable  
Standby  
Reset  
2
2
VIH  
VIH  
VIL  
VIH  
VIL  
VIH  
X
VIH  
X
VIH  
X
High Z  
High Z  
High Z  
DIN  
High Z  
High Z  
High Z  
DIN  
2, 7  
2, 5–7  
X
X
Write  
VIL  
VIH  
VIL  
NOTES:  
1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15]  
2. X must be VIL, VIH for control pins and addresses.  
3. See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, VPP4 voltages.  
4. Manufacturer and device codes may also be accessed in read identifier mode (A –A21 = 0). See Table 4.  
1
5. Refer to Table 6 for valid DIN during a write operation.  
6. To program or erase the lockable blocks, hold WP# at V .  
IH  
7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.  
12  
PRELIMINARY