Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.38
8.1.39
8.1.40
PRDY# (O - AGTL)
The PRDY# (Probe Ready) signal is a processor output used by debug tools to determine processor
debug readiness.
PREQ# (I - 1.5 V Tolerant)
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the
processor.
PWRGOOD (I – 1.8 V Tolerant)
PWRGOOD (Power Good) is a 1.8-V tolerant input. The processor requires this signal to be a
clean indication that clocks and the power supplies (VCC, VCCT, etc.) are stable and within their
specifications. Clean implies that the signal will remain low, (capable of sinking leakage current)
and without glitches, from the time that the power supplies are turned on, until they come within
specification. The signal will then transition monotonically to a high (1.8 V) state. Figure 12
through Figure 14 illustrate the relationship of PWRGOOD to other system signals. PWRGOOD
may be driven inactive at any time, but clocks and power must again be stable before the rising
edge of PWRGOOD. It must also meet the minimum pulse width specified in Table 25 (Section
3.6) and be followed by a 1 ms RESET# pulse.
The PWRGOOD signal, which must be supplied to the processor, is used to protect internal circuits
against voltage sequencing issues. The PWRGOOD signal should be driven high throughout
boundary scan operation.
8.1.41
8.1.42
REQ[4:0]# (I/O - AGTL)
The REQ[4:0]# (Request Command) signals must be connected to the appropriate pins/balls on
both agents on the system bus. They are asserted by the current bus owner when it drives A[35:3]#
to define the currently active transaction type.
RESET# (I - AGTL)
Asserting the RESET# signal resets the processor to a known state and invalidates the L1 and L2
caches without writing back Modified (M state) lines. For a power-on type reset, RESET# must
stay active for at least 1 ms after VCC and BCLK, BCLK# have reached their proper DC and AC
specifications and after PWRGOOD has been asserted. When observing active RESET#, all bus
agents will deassert their outputs within two clocks. RESET# is the only AGTL signal that does not
have on-die AGTL termination. A 56.2 Ω 1% terminating resistor connected to VCCT is required.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-
on configuration. The configuration options are described in Section 4.0 and in the P6 Family of
Processors Developer’s Manual.
Unless its outputs are tri-stated during power-on configuration, after an active-to-inactive transition
of RESET#, the processor optionally executes its built-in self-test (BIST) and begins program
execution at reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected to the
appropriate pins/balls on both agents on the system bus.
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Datasheet
INTEL [ INTEL ]
