Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.43
RP# (I/O - AGTL)
The RP# (Request Parity) signal is driven by the request initiator and provides parity protection on
ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on the
system bus.
A correct parity signal is high if an even number of covered signals is low and low if an odd
number of covered signals are low. This definition allows parity to be high when all covered
signals are high.
8.1.44
8.1.45
RS[2:0]# (I/O - AGTL)
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for
completion of the current transaction) and must be connected to the appropriate pins/balls on both
agents on the system bus.
RSP# (I - AGTL)
The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#. RSP# provides parity
protection for RS[2:0]#. RSP# should be connected to the appropriate pins/balls on both agents on
the system bus.
A correct parity signal is high if an even number of covered signals are low, and it is low if an odd
number of covered signals are low. During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also
high since it is not driven by any agent ensuring correct parity.
8.1.46
8.1.47
RTTIMPEDP (I-Analog)
The RTTIMPEDP (RTT Impedance/PMOS) signal is used to configure the on-die AGTL
termination. Connect the RTTIMPEDP signal to VSS with a 56.2-Ω, 1% resistor.
SMI# (I - 1.5 V Tolerant)
The SMI# (System Management Interrupt) is asserted asynchronously by system logic. On
accepting a System Management Interrupt, the processor saves the current state and enters System
Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins
program execution from the SMM handler.
8.1.48
STPCLK# (I - 1.5 V Tolerant)
The STPCLK# (Stop Clock) signal, when asserted, causes the processor to enter a low-power
Quick Start state. The processor issues a Stop Grant Acknowledge special transaction and stops
providing internal clock signals to all units except the bus and APIC units. The processor continues
to snoop bus transactions and service interrupts while in the Quick Start state. When STPCLK# is
deasserted and other conditions in are met, the processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has no affect on the bus clock.
Datasheet
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INTEL [ INTEL ]
