Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 45. Input Signals (Sheet 2 of 2)
Name
Active Level
Clock
Signal Group
Qualified
STPCLK#
TCK
Low
Asynch
—
Implementation
JTAG
Always
High
TDI
TCK
JTAG
TMS
TCK
JTAG
TRST#
VTTPWRGD
Low
Asynch
Asynch
JTAG
High
Power/Other
Table 46. Output Signals
Name
Active Level
Clock
Signal Group
BSEL[1:0]
FERR#
IERR#
High
Low
Low
Low
High
High
Asynch
Asynch
Asynch
BCLK
Open-drain
Open-drain
Open-drain
Implementation
JTAG
PRDY#
TDO
TCK
VID[4:0]
Asynch
Power/Other
Table 47. Input/Output Signals (Single Driver)
Name
Active Level
Clock
Signal Group
Qualified
A[35:3]#
ADS#
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
ADS#, ADS#+1
Always
AP[1:0]#
BREQ0#
BP[3:2]#
BPM[1:0]#
D[63:0]#
DBSY#
ADS#, ADS#+1
Always
Always
Always
DRDY#
Always
DEP[7:0]#
DRDY#
LOCK#
DRDY#
Always
Always
REQ[4:0]#
RP#
ADS#, ADS#+1
ADS#, ADS#+1
Always
RS[2:0]#
TRDY#
Response phase
80
Datasheet
INTEL [ INTEL ]
