Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.49
8.1.50
8.1.51
8.1.52
8.1.53
8.1.54
TCK (I - 1.5 V Tolerant)
The TCK (Test Clock) signal provides the clock input for the test bus (also known as the test access
port).
TDI (I - 1.5 V Tolerant)
The TDI (Test Data In) signal transfers serial test data to the processor. TDI provides the serial
input needed for JTAG support.
TDO (O - 1.5 V Tolerant Open-drain)
The TDO (Test Data Out) signal transfers serial test data from the processor. TDO provides the
serial output needed for JTAG support.
TESTHI[2:1] (I - 1.25 V Tolerant)
The TESTHI[2:1] (Test input High) signals are used during processor test and need to be pulled
high during normal operation.
TESTLO[2:1] (I - 1.5 V Tolerant)
The TESTLO[2:1] (Test input Low) signals are used during processor test and needs to be pulled to
ground during normal operation.
THERMDA, THERMDC (Analog)
The THERMDA (Thermal Diode Anode) and THERMDC (Thermal Diode Cathode) signals
connect to the anode and cathode of the on-die thermal diode.
8.1.55
8.1.56
TMS (I - 1.5 V Tolerant)
The TMS (Test Mode Select) signal is a JTAG support signal used by debug tools.
TRDY# (I/O - AGTL)
The TRDY# (Target Ready) signal is asserted by the target to indicate that the target is ready to
receive write or implicit write-back data transfer. TRDY# must be connected to the appropriate
pins/balls on both agents on the system bus.
8.1.57
TRST# (I - 1.5 V Tolerant)
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. The ULV Intel Celeron
processors do not self-reset during power on; therefore, it is necessary to drive this signal low
during power-on reset.
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Datasheet
INTEL [ INTEL ]
