Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 44 shows the encoding scheme for BSEL[1:0]. The only supported system bus frequency for
the ULV Intel® Celeron® processor is 100 MHz. If another frequency is used, then the processor is
not ensured to function properly.
Table 44. BSEL[1:0] Encoding
BSEL[1:0]
System Bus Frequency
01
100 MHz
8.1.15
8.1.16
CLKREF (Analog)
The CLKREF (System Bus Clock Reference) signal provides a reference voltage to define the trip
point for the BCLK signal on platforms supporting Single Ended Clocking. This signal should be
connected to a resistor divider to generate 1.25 V from the 2.5-V supply. A minimum of 1-µF
decoupling capacitance is recommended on CLKREF. On systems with Differential Clocking, the
CLKREF pin functions as the BCLK# input.
CMOSREF (Analog)
The CMOSREF (CMOS Reference Voltage) signal provides a DC level reference voltage for the
CMOS input buffers. CMOSREF must be generated from a stable 1.5V supply (815 chipset
family), 2.5 V (440MX chipset family) and must meet the VCMOSREF specification. The same
1.5 V (815 chipset family) or 2.5 V (440MX chipset family) supply should be used to power the
chipset CMOS I/O buffers that drive the CMOS signals. The Thevenin equivalent impedance of the
VCMOSREF generation circuits must be less than 0.5 K Ω/1 K Ω (i.e., top resistor 500 Ω, bottom
resistor 1 K Ω) for the Intel 815 Chipset family. The Thevenin equivalent impedance of the
VCMOSREF generation circuits must be less than 0.75 K Ω/0.5 K Ω (i.e., top resistor 750 Ω,
bottom resistor 500 Ω) for the Intel 440MX chipset family.
8.1.17
8.1.18
D[63:0]# (I/O - AGTL)
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between
both system bus agents, and must be connected to the appropriate pins/balls on both agents. The
data driver asserts DRDY# to indicate a valid data transfer.
DBSY# (I/O - AGTL)
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the
system bus to indicate that the data bus is in use. The data bus is released after DBSY# is
deasserted. This signal must be connected to the appropriate pins/balls on both agents on the
system bus.
8.1.19
DEFER# (I - AGTL)
The DEFER# (Defer) signal is asserted by an agent to indicate that the transaction cannot be
ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed
memory agent or I/O agent. This signal must be connected to the appropriate pins/balls on both
agents on the system bus.
72
Datasheet
INTEL [ INTEL ]
