Ultra-Low Voltage Intel
®
Celeron
®
Processor — 650 MHz and 400 MHz
1.0
Introduction
Using Intel’s advanced 0.13-micron process technology with copper interconnect, the Ultra-Low
Voltage Intel
®
Celeron
®
processor offers high-performance and low power consumption. The
Ultra-Low Voltage Intel Celeron processor (0.13µ) in the Micro FC-BGA packages (hereafter
referred to as the ULV Intel Celeron processor) is based on the same core as existing Intel
®
Pentium
®
III
processors. Key performance features include Internet Streaming SIMD instructions,
Advanced Transfer Cache architecture, and a processor system bus speed of 100 MHz. These
features are offered in a Micro FC-BGA packages for surface mount small form factor boards.
The 256-Kbyte integrated L2 cache based on the Advanced Transfer Cache architecture runs at full
speed and is designed to help improve performance. It complements the system bus by providing
critical data faster and reducing total system power consumption. The processor also features Data
Prefetch Logic that speculatively fetches data to the L2 cache, resulting in improved performance.
The Intel Celeron processor’s 64-bit wide Assisted Gunning Transceiver Logic (AGTL) system bus
provides a glueless, point-to-point interface for a memory controller hub.
This document covers the electrical, mechanical, and thermal specifications for the Ultra-Low
Voltage Intel Celeron processor at 650 MHz at 1.10 V and 400 MHz at 0.95 V.
1.1
Overview
•
Performance features
— Supports the Intel Architecture with Dynamic Execution
— Supports Intel MMX
™
technology
— Supports Streaming SIMD Extensions for enhanced video, sound, and 3D performance
— Integrated Intel Floating Point Unit compatible with the IEEE 754 standard
— Data Prefetch Logic
•
On-die primary (L1) instruction and data caches
— 4-way set associative, 32-byte line size, 1 line per sector
— 16-Kbyte instruction cache and 16-Kbyte write-back data cache
— Cacheable range controlled by processor programmable registers
•
On-die second level (L2) cache
— 8-way set associative, 32-byte line size, 1 line per sector
— Operates at full core speed
— 256-Kbyte ECC protected cache data array
•
AGTL system bus interface
— 64-bit data bus, 100-MHz
— Uniprocessor, two loads only (processor and chipset)
— Integrated termination
•
Processor clock control
Datasheet
9
INTEL [ INTEL CORPORATION ]
