System Bus Signal Quality Specifications
Figure 28. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers
Vcc
Threshold Region to switch
receiver to a logic 1.
Vt+ (max)
Vt+ (min)
0.5 * Vcc
Vt- (max)
Allowable Ringback
Vss
Figure 29. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers
Vcc
Allowable Ringback
Vt+ (min)
0.5 * Vcc
Vt- (max)
Vt- (min)
Threshold Region to switch
receiver to a logic 0.
Vss
54
Mobile Intel Pentium 4 Processor-M Datasheet