Electrical Specifications
Table 11. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Battery Optimized Mode
(VID = 1.20 V, VID Offset = 4.62%)
VCC Nominal
(V)
VCC Static Min VCC Static Max
VCC Transient
Min (V)
VCC Transient
Max (V)
ICC (A)
(V)
(V)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
1.145
1.143
1.141
1.139
1.137
1.135
1.133
1.131
1.129
1.120
1.118
1.116
1.114
1.112
1.110
1.108
1.106
1.104
1.170
1.168
1.166
1.164
1.162
1.160
1.158
1.156
1.154
1.100
1.098
1.096
1.094
1.092
1.090
1.088
1.086
1.084
1.190
1.188
1.186
1.184
1.182
1.180
1.178
1.176
1.174
Figure 6. Illustration of Deep Sleep V Static and Transient Tolerances (VID Setting = 1.30 V)
CC
Northwood Deep Sleep Load Line for VID = 1.30V
1.300
Transient Maximum
1.280
Static Maximum
1.260
Vcc Nominal
1.240
1.220
1.200
Static Minimum
1.180
Transient Minimum
1.160
1.140
1.120
0
1
2
3
4
5
6
7
8
9
10
Isb Maximum
Mobile Intel Pentium 4 Processor-M Datasheet
29
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