欢迎访问ic37.com |
会员登录 免费注册
发布采购

21150-AB 参数 Datasheet PDF下载

21150-AB图片预览
型号: 21150-AB
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PQFP208, PLASTIC, QFP-208]
分类和应用: 时钟PC外围集成电路
文件页数/大小: 164 页 / 811 K
品牌: INTEL [ INTEL ]
 浏览型号21150-AB的Datasheet PDF文件第21页浏览型号21150-AB的Datasheet PDF文件第22页浏览型号21150-AB的Datasheet PDF文件第23页浏览型号21150-AB的Datasheet PDF文件第24页浏览型号21150-AB的Datasheet PDF文件第26页浏览型号21150-AB的Datasheet PDF文件第27页浏览型号21150-AB的Datasheet PDF文件第28页浏览型号21150-AB的Datasheet PDF文件第29页  
21150  
2.8  
JTAG Signals  
Table 11 describes the JTAG signals.  
Table 11. JTAG Signals  
Signal Name  
Type  
Description  
JTAG serial data in. Signal tdi is the serial input through which  
JTAG instructions and test data enter the JTAG interface. The  
new data on tdi is sampled on the rising edge of tck. An  
unterminated tdi produces the same result as if tdi were driven  
high.  
tdi  
I
JTAG serial data out. Signal tdo is the serial output through  
which test instructions and data from the test logic leave the  
21150.  
tdo  
O
JTAG test mode select. Signal tms causes state transitions in  
the test access port (TAP) controller. An undriven tms has the  
same result as if it were driven high.  
tms  
tck  
I
I
JTAG boundary-scan clock. Signal tck is the clock controlling  
the JTAG logic.  
JTAG TAP reset. When asserted low, the TAP controller is  
asynchronously forced to enter a reset state, which in turn  
asynchronously initializes other test logic. An unterminated  
trst_l produces the same result as if it were driven high.  
trst_l  
I
Preliminary Datasheet  
17  
 
 复制成功!