21150
4.5.2
Memory Write and Invalidate Transactions
Posted write forwarding is used for memory write and invalidate transactions. Memory write and
invalidate transactions guarantee transfer of entire cache lines. If the write buffer fills before an
entire cache line is transferred, the 21150 disconnects the transaction and converts it to a memory
write transaction.
The 21150 disconnects memory write and invalidate commands at aligned cache line boundaries.
The cache line size value in the 21150 cache line size register gives the number of Dwords in a
cache line. For the 21150 to generate memory write and invalidate transactions, this cache line size
value must be written to a value that is a nonzero power of 2 and less than or equal to 16 (that is, 1,
2, 4, 8, or 16 Dwords).
If the cache line size does not meet the memory write and invalidate conditions, that is, the value is
0, or is not a power of 2, or is greater than 16 Dwords, the 21150 treats the memory write and
invalidate command as a memory write command. In this case, when the 21150 forwards the
memory write and invalidate transaction to the target bus, it converts the command code to a
memory write code and does not observe cache line boundaries.
If the value in the cache line size register does meet the memory write and invalidate conditions,
that is, the value is a nonzero power of 2 less than or equal to 16 Dwords, the 21150 returns a target
disconnect to the initiator either on a cache line boundary or when the posted write buffer fills. For
a cache line size of 16 Dwords, the 21150 disconnects a memory write and invalidate transaction
on every cache line boundary. When the cache line size is 1, 2, 4, or 8 Dwords, the 21150 accepts
another cache line if at least 8 Dwords of empty space remains in the posted write buffer. If less
than 8 Dwords of empty space remains, the 21150 disconnects on that cache line boundary.
When the memory write and invalidate transaction is disconnected before a cache line boundary is
reached, typically because the posted write buffer fills, the transaction is converted to a memory
write transaction.
4.5.3
Delayed Write Transactions
Delayed write forwarding is used for I/O write transactions and for Type 1 configuration write
transactions.
A delayed write transaction guarantees that the actual target response is returned back to the
initiator without holding the initiating bus in wait states. A delayed write transaction is limited to a
single Dword data transfer.
When a write transaction is first detected on the initiator bus, and the 21150 forwards it as a
delayed transaction, the 21150 claims the access by asserting DEVSEL# and returns a target retry
to the initiator. During the address phase, the 21150 samples the bus command, address, and
address parity one cycle later. After IRDY# is asserted, the 21150 also samples the first data
Dword, byte enable bits, and data parity. This information is placed into the delayed transaction
queue. The transaction is queued only if no other existing delayed transactions have the same
address and command, and if the delayed transaction queue is not full. When the delayed write
transaction moves to the head of the delayed transaction queue and all ordering constraints with
posted data are satisfied (see Section 6.0), the 21150 initiates the transaction on the target bus. The
21150 transfers the write data to the target. If the 21150 receives a target retry in response to the
write transaction on the target bus, it continues to repeat the write transaction until the data transfer
is completed, or until an error condition is encountered.
32
Preliminary Datasheet
INTEL [ INTEL ]
