A10-DATASHEET
2015.12.31
73
NAND Timing Characteristics
NAND Timing Characteristics
Table 71: NAND ONFI 1.0 Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
10
7
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(91)
tWP
Write enable pulse width
Write enable hold time
Read enable pulse width
Read enable hold time
(91)
tWH
—
(91)
tRP
10
7
—
(91)
tREH
—
(91)
tCLS
Command latch enable to write enable setup time
Command latch enable to write enable hold time
Chip enable to write enable setup time
Chip enable to write enable hold time
Address latch enable to write enable setup time
Address latch enable to write enable hold time
Data to write enable setup time
10
5
—
(91)
tCLH
—
(91)
tCS
15
5
—
(91)
tCH
—
(91)
(91)
tALS
10
5
—
tALH
—
(91)
tDS
7
—
(91)
tDH
Data to write enable hold time
5
—
tCEA
tREA
tRHZ
tRR
Chip enable to data access time
—
—
—
20
—
100
40
200
—
Read enable to data access time
Read enable to data high impedance
Ready to read enable low
(91)
tWB
Write enable high to R/B low
200
(91)
This timing is software programmable.
Arria 10 Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
