A10-DATASHEET
2015.12.31
71
I2C Timing Characteristics
I2C Timing Characteristics
Table 70: I2C Timing Requirements for Arria 10 Devices—Preliminary
Standard Mode
Fast Mode
Symbol
Description
Unit
Min
Max
—
Min
2.5
0.6
1.3
0.1
Max
—
Tclk
Serial clock (SCL) clock period
SCL high period
10
4
μs
μs
μs
μs
tHIGH
tLOW
tSU;DAT
—
—
SCL low period
4.7
0.25
—
—
Setup time for serial data line (SDA) data to
SCL
—
—
(89)
tHD;DAT
Hold time for SCL to SDA data
SCL to SDA output data delay
0
3.15
3.45
0
0.6
0.9
μs
μs
tVD;DAT
and
—
—
tVD;ACK
tSU;STA
tHD;STA
tSU;STO
tBUF
Setup time for a repeated start condition
Hold time for a repeated start condition
Setup time for a stop condition
4.7
4
—
—
—
—
0.6
0.6
0.6
1.3
—
—
—
—
μs
μs
μs
μs
4
SDA high pulse duration between STOP and
START
4.7
tr
tf
SCL rise time
SCL fall time
—
—
1000
300
20
300
300
ns
ns
20 × (Vdd
5.5) (90)
/
/
tr
tf
SDA rise time
SDA fall time
—
—
1000
300
20
300
300
ns
ns
20 × (Vdd
5.5) (90)
(89)
(90)
You must enable an internal delay in the embedded software. The delay is programmable using the ic_sda_holdregister in the I2C controller.
Vdd is the I2C bus voltage.
Arria 10 Device Datasheet
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