A10-DATASHEET
2015.12.31
46
Periphery Performance Specifications
Parameter
Minimum
Typical
—
Maximum
1.5
Unit
V
Input signal range for Vsigp
0
0
0
Unipolar Input
Mode
Common mode voltage on Vsign
Input signal range for Vsigp – Vsign
—
0.25
V
—
1.25
V
Periphery Performance Specifications
This section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/
IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Table 46: High-Speed I/O Specifications for Arria 10 Devices—Preliminary
When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block.
For LVDS applications, you must use the PLLs in integer PLL mode.
You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
–E1L, –E1M (64), –E1S, –I1L,
–I1M (64), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (65), –I1M (65), –E3S,
–I3S
Symbol
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fHSCLK_in (input clock frequency)
True Differential I/O Standards
Clock boost
factor
10
—
800
10
—
700
10
—
625
MHz
W = 1 to 40 (66)
(64)
(65)
(66)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
Arria 10 Device Datasheet
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