IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
DMA Count Register (FIFO):
The FIFO register is actually three registers that make a three byte FIFO. These are used as
temporary storage between the eight bit shift register and the receive buffer when an information
field is received. This register is an ICE support register. FIFO is byte addressable.
FIFO
Bit: 7
6
5
4
3
2
1
0
FIFO*.7
FIFO*.6
FIFO*.5
FIFO*.4
FIFO*.3
FIFO*.2
FIFO*.1
FIFO*.0
* = 1, 2 or 3 for FIFO1, FIFO2, FIFO3 respectively.
SIU State Counter (SIUST):
The SIUST register indicates which state the SIU state machine is currently in. This in turn indicates
what task the SIU is performing or which field is expected next by the SIU. This register should not
be written to. This register is an ICE support register. SIUST is byte addressable.
SIUST
Bit: 7
6
5
4
3
2
1
0
SIUST .7 SIUST .6 SIUST .5 SIUST .4 SIUST .3 SIUST .2 SIUST .1 SIUST .0
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ENG210010112-00
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