IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
Transmit Buffer Start Address Register (TBS):
The TBS contains the address in internal RAM where the frame (starting with the I-field) to be
transmitted is stored. The CPU should access TBS only when the SIU is not transmitting a frame,
TBF = 0. TBS is byte addressable.
TBS
Bit: 7
6
5
4
3
2
1
0
TBS.7
TBS.6
TBS.5
TBS.4
TBS.3
TBS.2
TBS.1
TBS.0
Transmit Buffer Length Register (TBL):
The TBL contains the length, in number of bytes, of the I-field to be transmitted. TBL = 0 is valid
(no I-field). The CPU should access TBL only when the SIU is not transmitting a frame, TBF = 0.
The transmit buffer will not wrap around after address 191 (BFH). A buffer end is automatically
generated when address 191 is reached. TBL is byte addressable.
TBL
Bit: 7
6
5
4
3
2
1
0
TBL.7
TBL.6
TBL.5
TBL.4
TBL.3
TBL.2
TBL.1
TBL.0
Transmit Control Byte Register (TCB):
The TCB contains the byte to be placed in the control field of the transmitted frame during non-
AUTO mode transmission. The CPU should access TCB only when the SIU is not transmitting a
frame, TBF = 0. TCB is byte addressable.
TCB
Bit: 7
6
5
4
3
2
1
0
TCB.7
TCB.6
TCB.5
TCB.4
TCB.3
TCB.2
TCB.1
TCB.0
Receive Buffer Start Address Register (RBS):
The RBS contains the address in internal RAM where the frame (starting with the I-field) being
received is to be stored. The CPU should write RBS only when the SIU is not receiving a frame,
RBE = 0. RBS is byte addressable.
RBS
Bit: 7
6
5
4
3
2
1
0
RBS.7
RBS.6
RBS.5
RBS.4
RBS.3
RBS.2
RBS.1
RBS.0
Copyright 2003
innovASIC
ENG210010112-00
www.innovasic.com
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