IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
STS.6
STS.7
RBE
TBF
Receive buffer empty. RBE is set by the CPU when it is ready to
receive a frame or has just read the buffer. RBE is cleared by the
SIU when a frame has been received. Can be thought of as a Receive
Enable.
Transmit buffer full. TBF is set by the CPU to indicate that the
transmit buffer is ready and TBF is cleared by the SIU.
Send/Receive count register (NSNR):
The NSNR contains both the transmit and receive sequence numbers in addition to the tally error
indications. The CPU can read and write the STS. Accessing the STS by the CPU via 2 cycle
instructions (JBC bit,rel and MOV bit,C) should not be used. The SIU can read and write the
NSNR. The NS and NR counters are not used in non-AUTO mode. NSNR is bit addressable.
NSNR
Bit: 7
6
5
4
3
2
1
0
NS2
NS1
NS0
SES
NR2
NR1
NR0
SER
NSNR.0
NSNR.1
NSNR.2
NSNR.3
NSNR.4
SER
NR0
NR1
NR2
SES
Sequence error receive. NS (P) ? NR (S).
Receive sequence counter, Bit 0.
Receive sequence counter, Bit 1.
Receive sequence counter, Bit 2.
Sequence error send. NR (P) ? NS (S) and
NR (P) ? NS (S) + 1.
NSNR.5
NSNR.6
NSNR.7
NS0
NS1
NS2
Send sequence counter, Bit 0.
Send sequence counter, Bit 1.
Send sequence counter, Bit 2.
Station Address register (STAD):
The STAD contains the station address (node address) of the chip. The CPU can read or write
STAD but should access STAD only when RTS = 0 and RBE = 0. Normally STAD is accessed
only during initialization. STAD is byte addressable.
STAD
Bit: 7
6
5
4
3
2
1
0
STAD.7
STAD.6
STAD.5
STAD.4
STAD.3
STAD.2
STAD.1
STAD.0
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innovASIC
ENG210010112-00
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