IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
Receive Buffer Length Register (RBL):
The RBL contains the length, in number of bytes, of the I-field storage area in internal RAM. RBL
= 0 is valid (no I-field). The CPU should write RBL only when the SIU is not receiving a frame,
RBE = 0. The receive buffer will not wrap around after address 191 (BFH). A buffer end is
automatically generated when address 191 is reached. RBL is byte addressable.
RBL
Bit: 7
6
5
4
3
2
1
0
RBL.7
RBL.6
RBL.5
RBL.4
RBL.3
RBL.2
RBL.1
RBL.0
Receive Field Length Register (RFL):
The RFL contains the length, in number of bytes, of the I-field of the frame received and stored in
internal RAM. RFL = 0 is valid (no I-field). The CPU should access RFL only when the SIU is not
receiving a frame, RBE = 0. RFL is loaded by the SIU. RFL is byte addressable.
RFL
Bit:
7
6
5
4
3
2
1
0
RFL.7
RFL.6
RFL.5
RFL.4
RFL.3
RFL.2
RFL.1
RFL.0
Receive Control Byte Register (RCB):
The RCB contains the control field of the frame received and stored in internal RAM. RCB is only
readable by the CPU and the CPU should access RCB only when the SIU is not receiving a frame,
RBE = 0. RCB is loaded by the SIU. RCB is byte addressable.
RCB
Bit: 7
6
5
4
3
2
1
0
RCB.7
RCB.6
RCB.5
RCB.4
RCB.3
RCB.2
RCB.1
RCB.0
DMA Count Register (DMA CNT):
The DMA CNT register contains the number of bytes remaining for the information field currently
being used. This register is an ICE support register. DMA CNT is byte addressable.
DMA CNT
Bit: 7
DMA
CNT.7
6
DMA
CNT.6
5
4
DMA
CNT.4
3
DMA
CNT.3
2
1
0
DMA
CNT.0
DMA
CNT.5
DMA
CNT.2
DMA
CNT.1
Copyright 2003
innovASIC
ENG210010112-00
www.innovasic.com
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