IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
TCHSH (1) (2)
(3)
(4)
(5)
(7)
(6)
Figure 14. Interrupt Acknowledge Cycle Waveforms
Please note that pins indicated in the parentheses are for the IA188XL version.
Notes:
(1) The OEM part (80C186XL) operates differently in that it deasserts on the falling edge of CLKOUT.
(2) Status is inactive in the state preceding T4.
(3) The data hold time lasts only until INTA goes inactive, even if the INTA transition occurs prior to TCLDX (min).
(4) INTA occurs one clock later in Slave Mode.
(5) This applies when a write cycle is followed by an interrupt acknowledge cycle.
(6) LOCK is active upon T1 of the first interrupt acknowledge cycle, and inactive upon T2 of the second interrupt acknowledge
cycle.
(7) Changes in T-state preceding next bus cycle if followed by write.
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