IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
5.1.8 CDRAM (0e2h)
The Count for Dynamic RAM (CDRAM) Refresh Control Register determines the period
between refresh cycles. The CDRAM register is undefined at reset (see Table 24).
Table 24. Count for Dynamic RAM Refresh Control Register
15 14 13 12 11 10
9
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
RC [8–0]
Bits [15–9]—Reserved → These bits read back as 0.
Bits [8–0]—RC [8–0] → These bits hold the clock count interval between refresh cycles.
In power-save mode, the refresh counter value should be adjusted to account for the clock
divider value in SYSCON.
5.1.9 MDRAM (0e0h)
The Memory Partition for Dynamic RAM (MDRAM) Refresh Control Register holds the a19–
a13 address bits of the 20-bit base refresh address. The MDRAM register contains 0000h at
reset (see Table 25).
Table 25. Memory Partition for Dynamic RAM Refresh Control Register
15 14 13 12 11 10
9
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
M [6–0]
Bits [15–9]—M [6–0] → Upper bits corresponding to address bits a19–a13 of the 20-bit
memory refresh address. These bits are not available on the a19–a0 bus. When using
PSRAM mode, M6–M0 must be programmed to 0000000b.
Bits [8–0]—Reserved → These bits read back as 0.
5.1.10 D1CON (0dah) and D0CON (0cah)
DMA CONtrol Registers. DMA Control Registers control operation of the two DMA channels.
The D0CON and D1CON registers are undefined at reset, except ST which is set to 0 (see
Table 26).
Table 26. DMA Control Registers
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DM/IOn DDEC DINC SM/Ion SDEC SINC TC INT SYN1–SYN0 P TDRQ EXT CHG ST Bn/W
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