IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 19. Processor Release Level Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PRL [7–0]
RES
Bits [15–8]—PRL [7–0] → The latest Processor Release Level.
Processor
PRL Value Release Level
10h
11h
12h
13h
14h
A
B
C
D
E
Bits [7–0]—Reserved.
5.1.4 AUXCON (0f2h)
The AUXiliary CONfiguration Register configures the flow control signals for the asynchronous
serial ports. AUXCON controls data bus width (8- or 16-bit) for lower memory, middle
memory, and IO accesses and contains 0000h at reset (see Table 20).
Table 20. Auxiliary Configuration Register
15 14 13 12 11 10
RES
9
8
7
6
5
4
3
2
1
0
ENRX1 RTS1 ENRX0 RTS0 LSIZ MSIZ IOSIZ
Bit [15–7]—Reserved.
Bit [6]—ENRX1 → When set to 1, the cts1_n/enrx1_n pin functions as cts1_n. When 0,
it functions as enrx1_n.
Bit [5]—RTS1 → When set to 1, the rtr1_n/rts1_n pin functions as rts1_n. When 0, it
functions as rtr1_n.
Bit [4]—ENRX0 → When set to 1, the cts0_n/enrx0_n pin functions as cts0_n. When 0,
it functions as enrx0_n.
Bit [3]—RTS0 → When set to 1, the rtr0_n/rts0_n pin functions as rts0_n. When 0, it
functions as rtr0_n.
Bit [2]—LSIZ (IA186ES only) → When set to 1, 8-bit data accesses are performed in
lower chip-select (lcs_n) space. When 0, 16-bit data accesses are performed.
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