IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Bits [10–8]—Reserved.
Bits [7–0]—COUNT → Control the timeout period for the WDT as follows:
Ttimeout = 2 exponent/frequency
(Equation 1)
Where:
Ttimeout
= The WDT timeout period in seconds.
frequency = The processor frequency in hertz.
exponent = Is based upon count as shown below:
Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0] Exponent
0
X
X
X
X
X
X
X
1
0
X
X
X
X
X
X
1
0
X
X
X
X
X
1
0
X
X
X
X
1
0
0
0
0
X
X
X
1
0
0
0
0
0
X
X
1
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
NA
10
20
21
22
23
24
25
26
0
0
0
5.1.7 EDRAM (0e4h)
The Enable Dynamic RAM Refresh Control Register provides control and status for the refresh
counter. The EDRAM register contains 0000h at reset (see Table 23).
Table 23. Enable Dynamic RAM Refresh Control Register
15 14 13 12 11 10
EN
9
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
T [8–0]
Bit [15]—EN → When set to 1, the refresh counter is enabled and msc3_n is configured
to act as rfsh_n. Clearing EN clears the refresh counter and disables refresh requests.
The refresh address is unaffected by clearing EN.
Bits [14–9]—Reserved → These bits read back as 0.
Bits [8–0]—T [8–0] → These bits hold the current value of the refresh counter. These
bits are read-only.
®
IA211050902-19
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