XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.2
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). The EBC also controls accesses to resources connected to the on-chip
LXBus (MultiCAN and the USIC modules). The LXBus is an internal representation of
the external bus and allows accessing integrated peripherals and modules in the same
way as external components.
The EBC can be programmed either to Single Chip Mode when no external memory is
required, or to an external bus mode with the following possible selections1):
•
•
•
Address Bus Width with a range of 0 … 24-bit
Data Bus Width 8-bit or 16-bit
Bus Operation Multiplexed or Demultiplexed
The bus interface uses Port 10 and Port 2 for addresses and data. In the demultiplexed
bus modes, the lower addresses are separately output on Port 0 and Port 1. The number
of active segment address lines is selectable, restricting the external address space to
8 Mbytes … 64 Kbytes. This is required when interface lines shall be assigned to Port 2.
Up to 5 external CS signals (4 windows plus default) can be generated and output on
Port 4 in order to save external glue logic. External modules can directly be connected
to the common address/data bus and their individual select lines.
A HOLD/HLDA protocol is available for bus arbitration and allows the sharing of external
resources with other bus masters. The bus arbitration is enabled by software. After
enabling, pins P3.0 … P3.2 (BREQ, HLDA, HOLD) are automatically controlled by the
EBC. In Master Mode (default after reset) the HLDA pin is an output. In Slave Mode pin
HLDA is switched to input. This allows the direct connection of the slave controller to
another master controller without glue logic.
Important timing characteristics of the external bus interface have been made
programmable (via registers TCONCSx/FCONCSx) to allow the user the adaption of a
wide range of different types of memories and external peripherals.
Access to very slow memories or modules with varying access times is supported via a
particular ‘Ready’ function. The active level of the control input signal is selectable.
In addition, up to 4 independent address windows may be defined (via registers
ADDRSELx) which control accesses to resources with different bus characteristics.
These address windows are arranged hierarchically where window 4 overrides
window 3, and window 2 overrides window 1. All accesses to locations not covered by
these 4 address windows are controlled by TCONCS0/FCONCS0. The currently active
window can generate a chip select signal.
The external bus timing is related to the rising edge of the reference clock output
CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.
1) Bus modes are switched dynamically if several address windows with different mode settings are used.
Data Sheet
38
V0.91, 2007-02
Draft Version
INFINEON [ Infineon ]
