XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC228x is configured in a von Neumann architecture, which
means that all internal and external resources, such as code memory, data memory,
registers and I/O ports, are organized within the same linear address space.
Table 3
XC228x Memory Map
Address Area
Start Loc. End Loc. Area Size1)
Notes
IMB register space
FF’FF00H FF’FFFFH 256 Bytes
–
Reserved (Access trap) F0’0000H
Reserved for EPSRAM E9’0000H
FF’FEFFH <1 Mbyte
EF’FFFFH 448 Kbytes
E8’FFFFH 64 Kbytes
E7’FFFFH 448 Kbytes
E0’FFFFH 64 Kbytes
Minus IMB reg.
Mirrors EPSRAM
Flash timing
Mirrors PSRAM
Maximum speed
Emulated PSRAM
Reserved for PSRAM
Program SRAM
E8’0000H
E1’0000H
E0’0000H
Reserved for pr. mem. CC’0000H DF’FFFFH <1.25 Mbytes –
Program Flash 2
Program Flash 1
Program Flash 0
C8’0000H CB’FFFFH 256 Kbytes
C4’0000H C7’FFFFH 256 Kbytes
C0’0000H C3’FFFFH 256 Kbytes
–
–
2)
External memory area 40’0000H
Available Ext. IO area3) 20’5800H
BF’FFFFH 8 Mbytes
3F’FFFFH < 2 Mbytes
–
Minus USIC/CAN
USIC registers
20’4000H
20’0000H
20’57FFH
6 Kbytes
Accessed via EBC
MultiCAN registers
20’3FFFH 16 Kbytes
1F’FFFFH < 2 Mbytes
Accessed via EBC
External memory area 01’0000H
Minus segment 0
SFR area
00’FE00H 00’FFFFH 0.5 Kbyte
–
–
–
–
–
–
–
–
Dual-Port RAM
Reserved for DPRAM
ESFR area
00’F600H
00’F200H
00’F000H
00’E000H
00’A000H
00’8000H
00’FDFFH 2 Kbytes
00’F5FFH 1 Kbyte
00’F1FFH 0.5 Kbyte
00’EFFFH 4 Kbytes
00’DFFFH 16 Kbytes
00’9FFFH 8 Kbytes
00’7FFFH 32 Kbytes
XSFR area
Data SRAM
Reserved for DSRAM
External memory area 00’0000H
1) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
2) One 4-Kbyte sector reserved for internal use.
3) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Data Sheet
35
V0.91, 2007-02
Draft Version
INFINEON [ Infineon ]
