XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.3
Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
PSRAM
Flash/ROM
PMU
CPU
Prefetch
CSP
IP
VECSEG
TFR
2-Stage
Prefetch
Pipeline
Unit
CPUCON1
CPUCON2
Branch
Unit
5-Stage
Pipeline
Injection/
Exception
Handler
DPRAM
Return
Stack
FIFO
IFU
DPP0
IPIP
IDX0
IDX1
QX0
QX1
QR0
QR1
SPSEG
SP
CP
R15
DPP1
DPP2
DPP3
STKOV
STKUN
R15
R15
R14
R14
R15
R14
R14
GPRs
GPRs
GPRs
+/-
+/-
ADU
GPRs
R1
R0
R1
Division Unit
Multiply Unit
Bit-Mask-Gen.
Barrel-Shifter
R1
R0
Multiply
Unit
MRW
R1
R0
R0
MCW
MSW
MDC
PSW
RF
+/-
+/-
MDH
MDL
ONES
ALU
DSRAM
EBC
Peripherals
Buffer
WB
MAH
MAL
ZEROS
MAC
DMU
mca04917_x.vsd
Figure 4
CPU Block Diagram
Data Sheet
39
V0.91, 2007-02
Draft Version
INFINEON [ Infineon ]
