XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3
Functional Description
The architecture of the XC228x combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see Figure 3). This bus structure enhances the overall system performance
by enabling the concurrent operation of several subsystems of the XC228x.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC228x.
PSRAM
16/32/64 Kbytes
DPRAM
2 Kbytes
DSRAM
16 Kbytes
OCDS
Debug Support
Program Flash 0
256 Kbytes
EBC
LXBus Control
External Bus
Control
CPU
Program Flash 1
192/256 Kbytes
C166SV2 - Core
Program Flash 2
0/64/256 Kbytes
WDT
RTC
Oscillators/PLL, System Fct.
Clock, Reset, Power Control,
Stand-By RAM
Interrupt & PEC
Interrupt Bus
CCU63 ...
ADC1 ADC0 GPT
CC2
CCU60
USIC2 USIC1 USIC0 Multi
2 Ch., 2 Ch., 2 Ch., CAN
64 x 64 x 64 x
8-Bit/
10-Bit 10-Bit
8 Ch. 16 Ch.
8-Bit/
T2
T7
T8
T12
T13
T12
T13
T3
T4
Buffer Buffer Buffer
RS232, RS232, RS232,
LIN,
SPI,
LIN,
SPI,
LIN,
SPI,
T5
2/5ch.
T6
IIC, IIS IIC, IIS IIC, IIS
BRGen
P15
Port 5
16
P11
P10
16
P9
P8 P7 P6 P4
P3
P2
P1
8
P0
8
6
8
7
5
4
8
8
13
8
MC_XC2X_BLOCKDIAGRAM
Figure 3
Block Diagram
Data Sheet
34
V0.91, 2007-02
Draft Version
INFINEON [ Infineon ]
