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    TLD7002-16ES 参数 Datasheet PDF下载

    TLD7002-16ES图片预览
    型号： TLD7002-16ES
    PDF下载： 下载PDF文件 查看货源
    内容描述： [The TLD7002-16ES is a 16 channel device with integrated and protected output stages. It is designed to control LEDs with a current up to 76.5 mA as linear current sink (LCS). The power stages can be configured in parallel for higher load currents. Each individual power output stage is configured to a 6-bit current set value stored in the OTP. 16 independent and individual PWM configurations can be set. A high-speed lighting interface is used for device OTP programming, configuration, control and]
    分类和应用：
    文件页数/大小： 82 页 / 3105 K
    品牌： INFINEON [ Infineon ]
     浏览型号TLD7002-16ES的Datasheet PDF文件第65页浏览型号TLD7002-16ES的Datasheet PDF文件第66页浏览型号TLD7002-16ES的Datasheet PDF文件第67页浏览型号TLD7002-16ES的Datasheet PDF文件第68页浏览型号TLD7002-16ES的Datasheet PDF文件第70页浏览型号TLD7002-16ES的Datasheet PDF文件第71页浏览型号TLD7002-16ES的Datasheet PDF文件第72页浏览型号TLD7002-16ES的Datasheet PDF文件第73页  
    TLD7002-16ES  
    Datasheet  
    9 Communication interface  
    Table 36  
    Master request byte overview  
    Bits Type Description  
    Field  
    MRC  
    [7:6]  
    w
    Rolling Counter, 2 bit counter value, master needs to increment in every  
    data transmission  
    0x00 default (start) value  
    Data Length Code  
    Function  
    DLC  
    FUN  
    [5:3]  
    [2:0]  
    w
    w
    The bits DLC[5:3] represent the data length code and is defined as shown in the next table.  
    Table 37 DLC field overview  
    DLC - Data Length Code  
    data length in words - multiple of 2 bytes  
    D2  
    0
    D1  
    0
    D0  
    0
    0 words, 0 bytes  
    1 word, 2 bytes  
    0
    0
    1
    0
    1
    0
    2 words, 4 bytes  
    4 words, 8 bytes  
    8 words, 16 bytes  
    12 words, 24 bytes  
    16 words, 32 bytes  
    32 words, 64 bytes  
    0
    1
    1
    1
    0
    0
    1
    0
    1
    1
    1
    0
    1
    1
    1
    The bits FUN[2:0] represent the desired function request as listed in the table below.  
    Table 38  
    Function request field overview  
    Function bits  
    Function  
    F0  
    F2  
    0
    F1  
    0
    0
    1
    1
    0
    0
    1
    1
    0
    1
    0
    1
    0
    1
    0
    1
    Broadcast duty cycle synchronization  
    0
    Duty cycle shadow register update  
    Request diagnostics  
    Hardware control frame  
    Write register  
    0
    0
    1
    1
    Read register  
    1
    Power mode change  
    Reserved  
    1
    The device increments the 2-bit master rolling counter MRC counter on every received valid master request frame  
    despite the address field.  
    A MRC fail is detected if there is a mismatch between the received MRC and the internal MRC counter.  
    The internal MRC counter is loaded afer a mismatch condition with the received MRC.  
    Datasheet  
    69  
    Rev.1.00  
    2022-05-03  

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