TLD7002-16ES
Datasheet
9 Communication interface
9.1.11.9
SYNC_BREAK
The LCU can initiate a sync break to reset the protocol handler.
The device detects a sync break if the HSLI bus is dominant ≥ tSYNC_BREAK and then recessive again.
Every received sync break reset signal is counted by the device. The sync break counter is reset on a valid HSLI
communication frame.
tSYNC_BREAK can be configured by the OTP according to table below.
Table 31
tSYNC_BREAK configuration
Step
tSYNC_BREAK
100 µs
250 µs
750 µs
1 ms
0
1
2
3 (default)
If the sync break is detected a reset of the protocol handler is initiated where,
•
•
master rolling counter (MRC) and slave rolling counter (RC) is reset to its default value (0) and
all pending transmissions are interrupted.
If the sync break counter is equal to 6 the slave performs a reset of the devices and enters init mode afer tIDLE2INIT
time. This reset mechanism is available in init mode, active mode, fail-safe mode and OTP mode
9.1.11.10 Handling of invalid frame requests
The slave can receive invalid request frames from the LCU master. Potential root causes for invalid frames can be
- Programming error at the LCU
- Distorted communication
- Loss of synchronization between slave and LCU causing the interpretation of a data frame as slave request frame.
Following mechanisms are integrated to avoid, detect and report invalid master request frames:
•
In case of a valid frame but a CRC-8 error occurred, the slave reports an invalid received frame with ACK.TER = '1'
as described.
•
In case of an invalid frame or syntax error the slave ignores and discards the received frame.
In case of a CRC-8 error the slave reports an invalid received frame with ACK.TER = '1' . The received frame is discarded
and the communication watchdog is not served.
In case of an invalid frame error the slave ignores and discards the received frame and the time out watchdog is not
served. No feedback is given to the LCU to prevent further potential bus collision or loss of data frames.
An invalid frame is considered if
•
•
•
•
•
•
stop bit is low
unrecognized sync byte
unspecified register in REG_WRITE or REG_READ frames
unspecified DLC and FUN combination
wrong master rolling counter MRC
CRC-3 for master request error
Datasheet
66
Rev.1.00
2022-05-03
INFINEON [ Infineon ]
