TDA5235
Appendix
Register Description
A_PLLINTC1
Offset
059H
Reset Value
93H
PLL MMD Integer Value Register Channel 1
ꢀ
ꢃ
ꢈ
ꢁ
%$1'6(/
3//,17&ꢁ
Z
Z
Field
Bits
7:6
Type
Description
BANDSEL
w
Frequency Band Selection
00B not used
01B 915MHz/868MHz
10B 434MHz
11B 315MHz
Reset: 2H
PLLINTC1
5:0
w
SDPLL Multi Modulus Divider Integer Offset value for Channel 1
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13H
PLL Fractional Division Ratio Register 0 Channel 1
A_PLLFRAC0C1
Offset
Reset Value
F3H
PLL Fractional Division Ratio Register 0
Channel 1
05AH
ꢀ
ꢁ
3//)5$&ꢀ&ꢁ
Z
Field
Bits
Type
Description
PLLFRAC0C1 7:0
w
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3H
PLL Fractional Division Ratio Register 1 Channel 1
A_PLLFRAC1C1
Offset
Reset Value
07H
PLL Fractional Division Ratio Register 1
Channel 1
05BH
Data Sheet
224
V1.0, 2010-02-19
INFINEON [ Infineon ]
