TDA5235
Appendix
Register Description
ꢀ
ꢇ
ꢁ
6)53$*(
Z
8186('
ꢂ
Field
Bits
Type
Description
UNUSED
7:1
-
UNUSED
Reset: 00H
SFRPAGE
0
w
Selection of Register Page File (Configuration A..D) for SPI
communication
0B
1B
Page 0 (Config. A, start address: 000H)
Page 1 (Config. B, start address: 100H)
Reset: 0H
PP0 and PP1 Configuration Register
PPCFG0
Offset
081H
Reset Value
50H
PP0 and PP1 Configuration Register
ꢀ
ꢄ
ꢅ
ꢁ
33ꢁ&)*
33ꢀ&)*
Z
Z
Field
Bits
Type
Description
PP1CFG
7:4
w
Port Pin 1 Output Signal Selection
0000B CLK_OUT
0001B RX_RUN
0010B NINT
0011B LOW
0100B HIGH
0101B DATA
0110B DATA_MATCHFIL
0111B n.u.
1000B CH_DATA
1001B CH_STR
1010B RXD
1011B RXSTR
1100B n.u.
1101B n.u.
1110B n.u.
1111B n.u.
Reset: 5H
Data Sheet
226
V1.0, 2010-02-19
INFINEON [ Infineon ]
